SDI Gearbox / Converter Xilinx FPGA IP

The Omnitek SDI IP and other highly optimised FPGA IP Cores are building blocks that can be combined to provide SDI format gearbox and conversion functionality. Gearbox functionality allow any SDI video format of one link type for example quad link 3G-SDI to be converted to another link type with the same frame rate and colour space, for example 12G-SDI.

Conversion functionality allows the conversion of any SDI video link type, image size, frame rate or colour space to be converted to any other.

Omnitek provides a large range of complementary IP Cores for video processing and connection. These IP cores can be used individually or in combination to provide FPGA solutions for applications in broadcast, AV, aerospace/defence, medical and automotive industries. Omnitek IP Cores can be supplied as discrete blocks for inclusion in your own designs, as single chip solutions or Omnitek can provide a bespoke solution which can be tailored to your specific needs.

The following are some typical examples of the implementation of Omnitek’s IP Cores for SDI format Gearbox and conversion.

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Example of 4K60 2 Sample Interleave Gearbox

SMPTE SDI specification define the use of 2 sample interleave (2SI) as the method of encoding video for 4K and UHD TV over quad 3G-SDI and single link 6G-SDI or 12G-SDI links.

This diagram shows a typical implementation of Omnitek’s SDI IP to support 2 sample interleave SDI format gearbox functionality.

Here the SDI Rx IP is connected to a Gearbox block and the output of the Gearbox block is connected to the SDI Tx IP.

The IP blocks are configured by an on-chip processor (for example ARM or MicroBlaze). This allows the selection of the individual links that make up the SDI video signal and the SMPTE virtual video streams that are contained within each link.

The Gearbox re-orders the input video and ancillary data to the chosen output video format.

The Omnitek GT Cores simplify the connection of each SDI link’s serial data steam into parallel data ready for processing by the other IP blocks.

 

Example of 4K60 2SI + Square Division Gearbox

Early developers of 4K equipment adopted a square division approach to transferring 4K material over quad link 3G-SDI where each link is effectively a standard HD (1920x1080) image. Although square division was easier to adopt it is much harder to process and adds delay, hardware and cost.

This diagram shows a typical implementation of Omnitek’s SDI IP to support both square division and 2 sample interleave SDI format gearbox functionality.

Here the SDI Rx IP is connected to a 5 channel DMA block that allows the pixel data to be reordered (from example from square division to 2 sample interleave). The output of the DMA block is connected to the SDI IP.

The IP blocks are configured by an on-chip processor (for example ARM, MicroBlaze or any AXI4-Lite CPU). This allows the selection of the individual links that make up the SDI video signal and the SMPTE virtual video streams that are contained within each link.

The MIG (Memory Interface Generator) controls the DMA access to externally connected DDR memory.

 

Example of SDI Cross Converter

Where conversion from one SDI video format (link type, image size, frame rate and colour space) to another is required, the Omnitek OSVP (Omnitek Scalable Video Processor) IP Core can be used with the SDI IP Cores to allow image size, frame rate and colour space conversion.

This diagram shows a typical implementation of the Omnitek SDI IPand the OSVP IP Core to provide video format conversion functionality.

Here the SDI Rx IP is connected to the OSVP IP Core which allows the input video image to be re-sized, frame rate converted and colour space converted. The output of the OSVP IP Core is connected to the SDI Tx IP.

The MIG (Memory Interface Generator) controls the DMA access to externally connected DDR memory.

In all these examples the IP Blocks are controlled using an ARM processor, MicroBlaze or any AXI4-Lite CPU. This CPU runs code using Bare Metal or Linux Support libraries.

 

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